As everyone knows, a DC to DC converter may convert a DC input voltage to a DC output voltage with a different value.
FIG. 1 is a schematic diagram showing a conventional DC to DC converter. The DC to DC converter includes a control circuit 10, a gate driver circuit 20 and a power stage circuit 30. Generally, the control circuit 10 may receive a DC output voltage (Vout) generated by the power stage circuit 30 and generate a corresponding pulse width modulation (PWM) signal according to the change of the DC output voltage (Vout). In addition, the gate driver circuit 20 receives the PWM signal and converts the PWM signal to a first driving signal and a second driving signal to the power stage circuit 30, and the power stage circuit 30 may convert a DC input voltage (Vin) to the DC output voltage (Vout) according to the change of the first driving signal and the change of the second driving signal.
In addition, the gate driver circuit 20 includes a first driver 22 and a second driver 24. The first driver 22 receives the PWM signal and generates the first driving signal having the same phase as the PWM signal. The second driver 24 receives the PWM signal and generates the second driving signal having a phase opposite to that of the PWM signal.
In addition, the power stage circuit 30 includes an upper power transistor 32, a lower power transistor 34, an output inductor (Lo) and an output capacitor (Co). The drain of the upper power transistor 32 is connected to the DC input voltage (Vin), and the gate of the upper power transistor 32 receives the first driving signal. The drain of the lower power transistor 34 is connected to the source of the upper power transistor 32, the gate of the lower power transistor 34 receives the second driving signal, and the source of the lower power transistor 34 is connected to the ground (GND). A first terminal of the output inductor (Lo) is connected to source of the upper power transistor 32, and a second terminal of the output inductor (Lo) is an output terminal of the power stage circuit 30, which may output the DC output voltage (Vout). In addition, the two terminals of the output capacitor (Co) are connected between the output terminal and the ground terminal (GND) of the power stage circuit 30, respectively. Generally, when the DC input voltage (Vin) is higher than the DC output voltage (Vout); the DC to DC converter may be considered as a buck DC to DC converter.
When the DC to DC converter is a buck DC to DC converter, the first driving signal and the second driving signal generated by the gate driver circuit 20 may turn on the upper power transistor 32 and the lower power transistor 34, respectively. The upper power transistor 32 and the lower power transistor 34 cannot be turned on at the same time. That is, when the upper power transistor 32 is turned on, the lower power transistor 34 is turned off. At that moment, the second current (I2) is zero, and the output current (Iout) of the power stage circuit 30 is provided by the first current (I1) generated by turning on the upper power transistor 32. On the contrary, when the lower power transistor 34 is turned on, the upper power transistor 32 is turned off. At that moment, the first current (I1) is zero, and the output current (Tout) of the power stage circuit 30 is provided by the second current (I2) generated by turning on the lower power transistor 34. Generally, when the DC output voltage (Vout) received by the control circuit 10 is lower than a predetermined value (such as 3.3V); the pulse width of the PWM signal becomes wider. Thus, the first driving signal generated by the gate driver circuit 20 may control the upper power transistor 32 to be turned on for a longer time, and the second driving signal controls the lower power transistor 34 to be turned off for a longer time. On the contrary, when the DC output voltage (Vout) received by the control circuit 10 is higher than the predetermined value (such as 3.3V); the pulse width of the PWM signal becomes narrower. Thus, the first driving signal generated by the gate driver circuit 20 may control the upper power transistor 32 to be turned on for a shorter time, and the second driving signal may control the lower power transistor 34 to be turned off for a shorter time.
In addition, the control circuit 10 of the DC to DC converter has multiple control modes. A voltage mode, a current mode and a constant on-time mode are common control modes. The three control modes are illustrated in detail hereinafter, the structures of the gate driver circuit 20 and the power stage circuit 30 in the three modes are the same, and they are not illustrated for a concise purpose.
FIG. 2A is a schematic diagram showing the conventional DC to DC converter in the voltage mode. The DC to DC converter of the voltage mode includes a control circuit 210, a gate driver circuit 220 and a power stage circuit 230. The control circuit 210 includes an error amplifier 212, a modulator 214, and a signal generator 216. The error amplifier 212 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 212 may compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the modulator 214.
In addition, the signal generator 216 may output a sawtooth waveform signal (ramp) with a first frequency to the modulator 214 to make the modulator 214 generate the PWM signal according to the compensation signal (comp) and the sawtooth waveform signal (ramp). Besides the sawtooth waveform signal (ramp), the signal generator 216 also may output signals having other forms such as a triangle waveform signal.
FIG. 2B is a schematic diagram showing the compensation signal (comp), the sawtooth waveform signal (ramp), the PWM signal, the first driving signal, and the second driving signal in the voltage mode. When the compensation signal (comp) is stronger than the sawtooth waveform signal (ramp), the PWM signal is in a high level. On the contrary, when the compensation signal (comp) is weaker than the sawtooth waveform signal (ramp), the PWM signal is in the lower level. Obviously, when the compensation signal (comp) changes, the pulse width of the PWM signal changes therewith. Furthermore, the first driving signal and the PWM signal have the same phase, and the second driving signal and the PWM signal have opposite phases. The frequency of the PWM signal and the frequency of the sawtooth waveform signal (ramp) are the first frequency.
FIG. 3A is a schematic diagram showing the conventional DC to DC converter in the current mode. The DC to DC converter in the current mode includes a control circuit 310, a gate driver circuit 320 and a power stage circuit 330. The control circuit 310 includes an error amplifier 312, a PWM comparator 313, a signal generator 314, a current sensing amplifier 315, an adder 316, and a set-reset (SR) latch 317. The error amplifier 312 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 312 may compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the PWM comparator 313.
Moreover, the current sensing amplifier 315 may detect the first current (I1) passing through the upper power transistor in the power stage circuit 330 or the second current (I2) passing through the lower power transistor. For example, the current sensing amplifier 315 may convert the first current (I1) passing through the upper power transistor to a sensing signal (Vsense).
In addition, the signal generator 314 may output a sawtooth waveform signal (ramp) and a clock signal (CLK) at the same time. The sawtooth waveform signal (ramp) and the clock signal (CLK) have the same first frequency. The sawtooth waveform signal (ramp) and the sensing signal (Vsense) are superposed by the adder 316 to be a sum signal (sum). The sum signal (sum) and the compensation signal (comp) are inputted to the PWM comparator 313. When the sum signal (sum) is stronger than the compensation signal (comp), the PWM comparator 313 may output a pulse wave to a reset terminal (R) of the SR latch 317. Furthermore, the clock signal (CLK) is inputted to a set terminal (S) of the SR latch 317. The PWM signal is generated according to the signal change of the reset terminal (R) and set terminal (S) of the SR latch. Besides the sawtooth waveform signal (ramp), the signal generator 314 also may output signals having other forms, such as the triangle waveform signal.
FIG. 3B is a schematic diagram showing the output current (Iout), the sensing signal (Vsense), the sawtooth waveform signal (ramp), the compensation signal (comp), the sum signal (sum), and the signals of the reset terminal (R) and the set terminal (S) of the SR latch, and the PWM signal of the DC to DC converter in the current mode.
The rising area of the output current (Iout) is the first current (I1) of the upper power transistor, and the falling area of the output current (Iout) is the second current (I2) of the lower power transistor. Therefore, the current sensing amplifier 315 may sense the first current (I1) to generate the sensing signal (Vsense). As shown in FIG. 3A and FIG. 3B, when the set terminal (S) of the SR latch receives the pulse wave, the PWM signal is in the high level, and when the reset terminal (R) of the SR latch receives a pulse wave, the PWM signal is in the low level. Therefore, the pulse width of the PWM signal changes with the value of the first current (I1).
FIG. 4A is a schematic diagram showing the conventional DC to DC converter in the constant on-time mode. The DC to DC converter in the constant on-time mode includes a control circuit 410, a gate driver circuit 420, and a power stage circuit 430. The control circuit 410 includes a loop comparator 412, a SR latch 414, and a timer 416. The timer 416 uses a constant current source (Ion) to charge a capacitor (Con), and the relationship between the charging voltage (Vcharge) and the constant current source (Ion) is
      V    charge    =            1      C        ⁢          ∫                        I          on                ⁢                              ⅆ            t                    .                    
That is, as long as the timer 416 starts, the charging process is started. When the charging voltage reaches a predetermined voltage, the timer 416 may output the pulse wave to the reset terminal (R) of the SR latch. Since the value of the constant current source (Ion) and the capacitance of the capacitor (Con) are constant, the time for the charging voltage to reach the predetermined voltage is fixed, which is a constant on-time Ton.
In addition, the loop comparator 412 receives the DC output voltage (Vout) and a reference voltage (Vref). When the DC output voltage (Vout) is lower than the reference voltage (Vref), the loop comparator 412 outputs the pulse wave to the set terminal (S) of the SR latch 414. When the loop comparator 412 outputs the pulse wave to the set terminal (S) of the SR latch 414, it also controls the timer 416 to count time. After the time Ton, a pulse wave is outputted to the reset terminal (R) of the SR latch 414. The PWM signal is generated according to the signal changes of the reset terminal (R) and set terminal (S) of the SR latch 414.
FIG. 4B is a schematic diagram showing the output voltage (Vout), the signals of the reset terminal (R) and set terminal (S) of the SR latch, and the PWM signal in the DC to DC converter in the constant on-time mode.
When the outputted voltage (Vout) is lower than the reference voltage, the set terminal (S) of the SR latch receives the pulse wave. After the time Ton, the timer 416 generates the pulse wave to the reset terminal (R) of the SR latch. As shown in FIG. 4A and FIG. 4B, when the set terminal (S) of the SR latch receives a pulse wave, the PWM signal is in the high level. When the reset terminal (R) of the SR latch receives the pulse wave, the PWM signal is in the low level.
As everyone knows, the operating voltages of a CPU, a DRAM, a graphic chip, and a chip set in a computer system are different. As a result, the computer system needs many DC to DC converters to convert the DC input voltage (such as 19V) provided by a power supply to the operating voltages for the components. However, the transient of the DC to DC converter may greatly influence the performance of the components.
When the load of the DC to DC converter changes greatly, the output current (Tout) changes rapidly. For example, when the output current (Tout) of the DC to DC converter decreases suddenly, the DC output voltage (Vout) increases quickly, which is called an overshoot. On the contrary, when the output current (Tout) of the DC to DC converter increases suddenly, the DC output voltage decreases quickly, which is called an undershoot.
When the overshoot or the undershoot is generated, the control circuit in the DC to DC converter should bring the over high or over low DC output voltage back to a voltage in a steady state. For example, when the overshoot happens, the transient DC output voltage is higher than the DC output voltage in the steady state. When the difference value between the transient DC output voltage and the DC output voltage is larger than a maximum value, the difference voltage between the transient DC output voltage and the DC output voltage is the overshoot voltage.
As shown in FIG. 5, if an operating frequency of the PWM signal of the DC to DC converter in the voltage mode is 200 KHz, and the DC output voltage in the steady state is 1.26V, when the output current decreases from 90 A to 5 A rapidly, the transient DC output voltage may increase to 1.36V. That is, the overshoot voltage is 100 mV. As shown in FIG. 6, if the operating frequency of the PWM signal of the DC to DC converter in the constant on-time mode is 276 KHz, and the DC output voltage in the steady state is 1.96V, when the output current decreases from 25 A to 1.5 A, the transient DC output voltage increases to 2.04V, and the overshoot voltage is 80 mV.
The designers of the DC to DC converter provide methods for improving the overshoot and undershoot. However, most designers designing the DC to DC converter improve the undershoot, and few people engages in the overshoot.
The U.S. Pat. No. 7,157,943 discloses a frequency selection of switch mode power converters via soft start voltage level. The switch mode power converter disclosed in the patent is described to be able to reduce the overshoot. However, the patent does not give out ideas about how to reduce the overshoot in application.
In addition, the Taiwan patent 1251395 discloses a PWM device for changing the output frequency automatically using an output voltage feedback hysteresis circuit. Obviously, the patent is disclosed to reduce the affection due to the loss of the upper power transistor or the lower power transistor. In addition, the PWM signal in the patent changes continuously. Therefore, the stableness of the DC to DC converter is worse.